10 search results - page 1 / 2 » Routing tree topology construction to meet interconnect timi... |
ISPD
1998
ACM
13 years 8 months ago
1998
ACM
DAC
2006
ACM
13 years 8 months ago
2006
ACM
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
The existence of non-uniform thermal gradients on the substrate in high performance IC’s can significantly impact the performance of global on-chip interconnects. This issue is...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
- This paper presents a solution to the problem of designing interconnects for memory devices. More precisely, it solves the automatic routing problem of memory peripheral circuits...
ICCAD
1997
IEEE
13 years 8 months ago
1997
IEEE
In this paper, we study the interconnect layout optimization problem under a higher-order RLC model to optimize not just delay, but also waveform for RLC circuits with non-monoton...