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» SAT-Based Algorithms for Logic Minimization
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TCAD
1998
86views more  TCAD 1998»
13 years 4 months ago
Fast heuristic and exact algorithms for two-level hazard-free logic minimization
None of the available minimizers for 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and auto...
Michael Theobald, Steven M. Nowick
IH
2004
Springer
13 years 10 months ago
Information Hiding in Finite State Machine
In this paper, we consider how to hide information into finite state machine (FSM), one of the popular computation models. The key advantage of hiding information in FSM is that t...
Lin Yuan, Gang Qu
ICCAD
1999
IEEE
84views Hardware» more  ICCAD 1999»
13 years 9 months ago
OPTIMISTA: state minimization of asynchronous FSMs for optimum output logic
The optimal state minimization problem is to select a reduced state machine having the best logic implementation over all possible state reductions and encodings. A recent algorit...
Robert M. Fuhrer, Steven M. Nowick
ASYNC
2001
IEEE
136views Hardware» more  ASYNC 2001»
13 years 9 months ago
Efficient Exact Two-Level Hazard-Free Logic Minimization
This paper presents a new approach to two-level hazardfree sum-of-products logic minimization. No currently available minimizers for single-output literal-exact two-level hazard-f...
Chris J. Myers, Hans M. Jacobson
FPGA
1992
ACM
176views FPGA» more  FPGA 1992»
13 years 9 months ago
Minimization of Permuted Reed-Muller Trees for Cellular Logic
The new family of Field Programmable Gate Arrays, CLI6000 from Concurrent Logic Inc realizes the truly Cellular Logic. It has been mainly designed for the realization of data path...
Li-Fei Wu, Marek A. Perkowski