14 search results - page 1 / 3 » SAT-based ATPG for Path Delay Faults in Sequential Circuits |
ICCAD
1999
IEEE
13 years 8 months ago
1999
IEEE
In this paper we present new methods for fast justification and propagation in the implication graph (IG) which is the core data structure of our SAT based implication engine. As ...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
MEMOCODE
2007
IEEE
13 years 10 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
ITC
2003
IEEE
13 years 9 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
JISE
2000
13 years 4 months ago
2000
We present an algorithm for identifyinga set of faults that do not have to be targeted by a sequential delay fault test generator. These faults either cannot independently aect th...