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2010
IEEE
263views Hardware» more  DATE 2010»
13 years 9 months ago
SCOC3: a space computer on a chip
—This paper presents the definition of an integrated processor core ASIC named SCOC3 which is designed for space computers. It also presents the validation method that has led to...
Franck Koebel, Jean-François Coldefy
IPPS
2006
IEEE
13 years 10 months ago
Multiprocessor on chip: beating the simulation wall through multiobjective design space exploration with direct execution
Design space exploration of multiprocessors on chip requires both automatic performance analysis techniques and efficient multiprocessors configuration performance evaluation. Pr...
Riad Ben Mouhoub, Omar Hammami
EUROPAR
2010
Springer
13 years 4 months ago
Power-Efficient Spilling Techniques for Chip Multiprocessors
Abstract. Current trends in CMPs indicate that the core count will increase in the near future. One of the main performance limiters of these forthcoming microarchitectures is the ...
Enric Herrero, José González, Ramon ...
HPCA
2011
IEEE
12 years 8 months ago
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...
Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tu...
VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 4 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture