12 search results - page 2 / 3 » SOC Test Architecture Optimization for Signal Integrity Faul... |
DAC
2001
ACM
14 years 5 months ago
2001
ACM
Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive ...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
In order to optimize interconnect to avoid signal integrity problems, very fast and accurate 3-D capacitance extraction is essential. Fast algorithms, such as the multipole or prec...
SAMOS
2004
Springer
13 years 10 months ago
2004
Springer
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level technique...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
ISCA
2010
IEEE
13 years 10 months ago
2010
IEEE
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...