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» SOC Testing Methodology and Practice
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DATE
2005
IEEE
160views Hardware» more  DATE 2005»
10 years 5 months ago
SOC Testing Methodology and Practice
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction...
Cheng-Wen Wu
DAC
2007
ACM
11 years 20 days ago
Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design
Due to shrinking technology, increasing functional frequency and density, and reduced noise margins with supply voltage scaling, the sensitivity of designs to supply voltage noise...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ISCAS
2008
IEEE
133views Hardware» more  ISCAS 2008»
10 years 6 months ago
A hybrid self-testing methodology of processor cores
—Software-based self-test (SBST) is a promising new technology for at-speed testing of embedded processors in SoC systems. This paper introduces an effective and efficient new ho...
Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee
ICCD
2005
IEEE
131views Hardware» more  ICCD 2005»
10 years 8 months ago
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs. It has been shown in recent prior work that the use of analog ...
Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
10 years 3 months ago
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses
Abstract--An integrated test scheduling methodology for multiprocessor System-on-Chips (SOC) utilizing the functional buses for test data delivery is described. The proposed method...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
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