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DATE
2002
IEEE
117views Hardware» more  DATE 2002»
13 years 10 months ago
Effective Software Self-Test Methodology for Processor Cores
Software self-testing for embedded processor cores based on their instruction set, is a topic of increasing interest since it provides an excellent test resource partitioning tech...
Nektarios Kranitis, Antonis M. Paschalis, Dimitris...
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
14 years 5 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 2 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
14 years 2 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
ASPDAC
2004
ACM
78views Hardware» more  ASPDAC 2004»
13 years 10 months ago
On compliance test of on-chip bus for SOC
- In this paper, we employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols,we proposea FSM model, which can help to extract the necess...
Hue-Min Lin, Chia-Chih Yen, Che-Hua Shih, Jing-Yan...