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DAC
1997
ACM
13 years 8 months ago
STARBIST: Scan Autocorrelated Random Pattern Generation
This paper presents a new scan-based BIST scheme which achieves very high fault coverage without the deficiencies of previously proposed schemes. This approach utilizes scan order...
Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, M...
IJNSEC
2010
98views more  IJNSEC 2010»
12 years 11 months ago
A Random Bit Generator Using Chaotic Maps
Chaotic systems have many interesting features such as sensitivity on initial condition and system parameter, ergodicity and mixing properties. In this paper, we exploit these int...
Narendra K. Pareek, Vinod Patidar, Krishan K. Sud
ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 8 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...
DATE
1999
IEEE
111views Hardware» more  DATE 1999»
13 years 8 months ago
Sequential Circuit Test Generation Using Decision Diagram Models
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
Jaan Raik, Raimund Ubar
ATS
2005
IEEE
191views Hardware» more  ATS 2005»
13 years 10 months ago
Low Transition LFSR for BIST-Based Applications
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed