5 search results - page 1 / 1 » STEFAL: A System Level Temperature- and Floorplan-Aware Leak... |
VLSID
2007
IEEE
13 years 10 months ago
2007
IEEE
In this paper we demonstrate the impact of the floorplan on the temperature-dependent leakage power of a System on Chip (SoC). We propose a novel system level temperature aware a...
ASPDAC
2007
ACM
13 years 8 months ago
2007
ACM
Abstract-- Process scaling and higher leakage power have resulted in increased power densities and elevated die temperatures. Due to the interdependence of temperature and leakage ...
TVLSI
2010
12 years 11 months ago
2010
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
CODES
2006
IEEE
13 years 10 months ago
2006
IEEE
Multi-million gate System-on-Chip (SoC) designs increasingly rely on Intellectual Property (IP) blocks. However, due to technology scaling the leakage power consumption of the IP ...
VLSID
2008
IEEE
13 years 10 months ago
2008
IEEE
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...