12 search results - page 3 / 3 » Scalable Cache Miss Handling for High Memory-Level Paralleli... |
ISHPC
2003
Springer
13 years 10 months ago
2003
Springer
We developed a multithreaded parallel implementation of a sequence alignment algorithm that is able to align whole genomes with reliable output and reasonable cost. This paper pres...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
Multi-core processors naturally exploit thread-level parallelism (TLP). However, extracting instruction-level parallelism (ILP) from individual applications or threads is still a ...