42 search results - page 9 / 9 » Scalable Hardware Memory Disambiguation for High ILP Process... |
SC
2009
ACM
13 years 10 months ago
2009
ACM
It has been shown that the sparse grid combination technique can be a practical tool to solve high dimensional PDEs arising in multidimensional option pricing problems in finance...
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of...