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DATE
2010
IEEE
148views Hardware» more  DATE 2010»
13 years 10 months ago
Scalable stochastic processors
Abstract—Future microprocessors increasingly rely on an unreliable CMOS fabric due to aggressive scaling of voltage and frequency, and shrinking design margins. Fortunately, many...
Sriram Narayanan, John Sartori, Rakesh Kumar, Doug...
ICPADS
1994
IEEE
13 years 9 months ago
Stochastic Modeling of Scaled Parallel Programs
Testingthe performance scalabilityof parallelprograms can be a time consuming task, involving many performance runs for different computer configurations, processor numbers, and p...
Allen D. Malony, Vassilis Mertsiotakis, Andreas Qu...
SIPS
2008
IEEE
13 years 11 months ago
Efficient mapping of advanced signal processing algorithms on multi-processor architectures
Modern microprocessor technology is migrating from simply increasing clock speeds on a single processor to placing multiple processors on a die to increase throughput and power pe...
Bhavana B. Manjunath, Aaron S. Williams, Chaitali ...
QEST
2010
IEEE
13 years 2 months ago
On the Theory of Stochastic Processors
Traditional architecture design approaches hide hardware uncertainties from the software stack through overdesign, which is often expensive in terms of power consumption. The recen...
Parasara Sridhar Duggirala, Sayan Mitra, Rakesh Ku...
ASPLOS
2004
ACM
13 years 10 months ago
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
Multiple Clock Domain (MCD) processors are a promising future alternative to today’s fully synchronous designs. Dynamic Voltage and Frequency Scaling (DVFS) in an MCD processor ...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...