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» Scaling, Power and the Future of CMOS
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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
13 years 11 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
SC
2000
ACM
13 years 10 months ago
Performance of Hybrid Message-Passing and Shared-Memory Parallelism for Discrete Element Modeling
The current trend in HPC hardware is towards clusters of shared-memory (SMP) compute nodes. For applications developers the major question is how best to program these SMP cluster...
D. S. Henty
BMCBI
2007
108views more  BMCBI 2007»
13 years 6 months ago
Publishing perishing? Towards tomorrow's information architecture
Scientific articles are tailored to present information in human-readable aliquots. Although the Internet has revolutionized the way our society thinks about information, the trad...
Michael R. Seringhaus, Mark B. Gerstein
CORR
2010
Springer
113views Education» more  CORR 2010»
13 years 6 months ago
Multi-core: Adding a New Dimension to Computing
Invention of Transistors in 1948 started a new era in technology, called Solid State Electronics. Since then, sustaining development and advancement in electronics and fabrication ...
Md. Tanvir Al Amin
CAL
2007
13 years 6 months ago
Logic-Based Distributed Routing for NoCs
—The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. ...
José Flich, José Duato