Sciweavers

17 search results - page 3 / 4
» Scheduling Reusable Instructions for Power Reduction
Sort
View
ISCA
2005
IEEE
166views Hardware» more  ISCA 2005»
13 years 11 months ago
Increased Scalability and Power Efficiency by Using Multiple Speed Pipelines
One of the most important problems faced by microarchitecture designers is the poor scalability of some of the current solutions with increased clock frequencies and wider pipelin...
Emil Talpes, Diana Marculescu
DAGSTUHL
2007
13 years 7 months ago
Compiler-based Software Power Peak Elimination on Smart Card Systems
Abstract. RF-powered smart cards are widely used in different application areas today. For smart cards not only performance is an important attribute, but also the power consumed ...
Matthias Grumer, Manuel Wendt, Christian Steger, R...
RTSS
1998
IEEE
13 years 10 months ago
Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors
The energy efficiency of systems-on-a-chip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systems-...
Inki Hong, Gang Qu, Miodrag Potkonjak, Mani B. Sri...
DATE
2007
IEEE
105views Hardware» more  DATE 2007»
14 years 2 days ago
Instruction-set customization for real-time embedded systems
Application-specific customization of the instruction set helps embedded processors achieve significant performance and power efficiency. In this paper, we explore customizatio...
Huynh Phung Huynh, Tulika Mitra
IISWC
2008
IEEE
14 years 4 days ago
Energy-aware application scheduling on a heterogeneous multi-core system
Heterogeneous multi-core processors are attractive for power efficient computing because of their ability to meet varied resource requirements of diverse applications in a workloa...
Jian Chen, Lizy Kurian John