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» Search-Space Optimizations for High-Level ATPG
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MTV
2005
IEEE
81views Hardware» more  MTV 2005»
10 years 1 months ago
Search-Space Optimizations for High-Level ATPG
Our mutation based validation paradigm (MVP) is a validation environment for high-level microprocessor implementations. To be able to efficiently identify and analyze the architec...
Jorge Campos, Hussain Al-Asaad
FPGA
2016
ACM
83views FPGA» more  FPGA 2016»
4 years 4 months ago
GPU-Accelerated High-Level Synthesis for Bitwidth Optimization of FPGA Datapaths
Bitwidth optimization of FPGA datapaths can save hardware resources by choosing the fewest number of bits required for each datapath variable to achieve a desired quality of resul...
Nachiket Kapre, Deheng Ye
DATE
2007
IEEE
72views Hardware» more  DATE 2007»
10 years 2 months ago
The impact of loop unrolling on controller delay in high level synthesis
Loop unrolling is a well-known compiler optimization that can lead to significant performance improvements. When used in High Level Synthesis (HLS) unrolling can affect the contr...
Srikanth Kurra, Neeraj Kumar Singh, Preeti Ranjan ...
GECCO
2009
Springer
146views Optimization» more  GECCO 2009»
10 years 2 months ago
Analyzing the landscape of a graph based hyper-heuristic for timetabling problems
Hyper-heuristics can be thought of as “heuristics to choose heuristics”. They are concerned with adaptively finding solution methods, rather than directly producing a solutio...
Gabriela Ochoa, Rong Qu, Edmund K. Burke
IWPC
2000
IEEE
10 years 9 days ago
A Pattern Matching Framework for Software Architecture Recovery and Restructuring
This paper presents a framework for software architecture recovery and restructuring. The user specifies a high level abstraction view of the system using a structured pattern la...
Kamran Sartipi, Kostas Kontogiannis, Farhad Mavadd...
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