At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
Susmita Sur-Kolay, Marly Roncken, Ken S. Stevens, ...
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
Mitchell A. Thornton, Kenneth Fazel, Robert B. Ree...
Abstract. We propose an asynchronous protocol for general multiparty computation with perfect security and communication complexity O(n2 |C|k) where n is the number of parties, |C|...
: This thesis focuses on the practical aspects of general two-party Secure Function Evaluation (SFE). A new SFE protocol that allows free evaluation of XOR gates and is provably se...
Abstract. We consider general secure function evaluation (SFE) of private functions (PF-SFE). Recall, privacy of functions is often most efficiently achieved by general SFE [18,19,...