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IPPS
1999
IEEE
13 years 8 months ago
Segment Directory Enhancing the Limited Directory Cache Coherence Schemes
We present a new arrangement of directory bits called the segment directory to improve directory storage efficiency: a segment directory can point to several sharing processors wi...
Jong Hyuk Choi, Kyu Ho Park
ASPLOS
1991
ACM
13 years 8 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
ICPP
1990
IEEE
13 years 8 months ago
Reducing Memory and Traffic Requirements for Scalable Directory-Based Cache Coherence Schemes
As multiprocessors are scaled beyond single bus systems, there is renewed interest in directory-based cache coherence schemes. These schemes rely on a directory to keep track of a...
Anoop Gupta, Wolf-Dietrich Weber, Todd C. Mowry
TC
2010
13 years 2 months ago
PERFECTORY: A Fault-Tolerant Directory Memory Architecture
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
Hyunjin Lee, Sangyeun Cho, Bruce R. Childers