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» Selecting partial scan flip-flops for circuit partitioning
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DATE
1998
IEEE
82views Hardware» more  DATE 1998»
13 years 8 months ago
Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection
Partial Scan techniques have been widely accepted as an effective solution to improve sequential ATPG performance while keeping acceptable area and performance overheads. Several ...
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
ICCAD
1994
IEEE
112views Hardware» more  ICCAD 1994»
13 years 8 months ago
Selecting partial scan flip-flops for circuit partitioning
This paper presents a new method of selecting scan ipops (FFs) in partial scan designs of sequential circuits. Scan FFs are chosen so that the whole circuit can be partitioned in...
Toshinobu Ono
IJFCS
1998
67views more  IJFCS 1998»
13 years 3 months ago
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits
Directed acyclic graphs (dags) are often used to model circuits. Path lengths in such dags represent circuit delays. In the vertex splitting problem, the objective is to determine...
Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni
ET
2000
73views more  ET 2000»
13 years 4 months ago
Deterministic BIST with Partial Scan
An efficient deterministic BIST scheme based on partial scan chains together with a scan selection algorithm tailored for BIST is presented. The algorithm determines a minimum num...
Gundolf Kiefer, Hans-Joachim Wunderlich
ASPDAC
1995
ACM
130views Hardware» more  ASPDAC 1995»
13 years 7 months ago
Design for testability using register-transfer level partial scan selection
Abstract - An approach to top down design for testability using register-transfer level(RTL) partial scan selection is described. We propose a scan selection technique based on tes...
Akira Motohara, Sadami Takeoka, Toshinori Hosokawa...