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DFT
2006
IEEE
203views VLSI» more  DFT 2006»
9 years 8 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...
VTS
2002
IEEE
113views Hardware» more  VTS 2002»
9 years 7 months ago
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects
For deep sub-micron system-on-chips (SoC), interconnects are critical determinants of performance, reliability and power. Buses and long interconnects being susceptible to crossta...
Krishna Sekar, Sujit Dey
DATE
2008
IEEE
112views Hardware» more  DATE 2008»
9 years 9 months ago
An novel Methodology for Reducing SoC Test Data Volume on FPGA-based Testers
Low-Cost test methodologies for Systems-on-Chip are increasingly popular. They dictate which features have to be included on-chip and which test procedures have to be adopted in o...
Paolo Bernardi, Matteo Sonza Reorda
DFT
2006
IEEE
105views VLSI» more  DFT 2006»
9 years 8 months ago
Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinge...
DDECS
2008
IEEE
184views Hardware» more  DDECS 2008»
9 years 9 months ago
Software-Based Self-Test Strategy for Data Cache Memories Embedded in SoCs
— Testing SoC is a challenging task, especially when addressing complex and highfrequency devices. Among the different techniques that can be exploited, Software-Based Selft-Test...
Wilson J. Perez, Jaime Velasco-Medina, Danilo Ravo...
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