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ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
13 years 9 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...
INFOCOM
2005
IEEE
13 years 11 months ago
Optimal fixed and scalable energy management for wireless networks
— In many devices, wireless network interfaces consume upwards of 30% of scarce portable system energy. Extending the system lifetime by minimizing communication power consumptio...
Rahul Mangharam, Ragunathan Rajkumar, Sofie Pollin...
ARVLSI
1997
IEEE
104views VLSI» more  ARVLSI 1997»
13 years 9 months ago
A High-Speed Asynchronous Decompression Circuit for Embedded Processors
This paper describes the architecture and implementation of a high-speed decompression engine for embedded processors. The engine is targeted to processors where embedded programs...
Martin Benes, Andrew Wolfe, Steven M. Nowick
TIP
2002
114views more  TIP 2002»
13 years 4 months ago
New architecture for dynamic frame-skipping transcoder
Abstract--Transcoding is a key technique for reducing the bitrate of a previously compressed video signal. A high transcoding ratio may result in an unacceptable picture quality wh...
Kai-Tat Fung, Yui-Lam Chan, Wan-Chi Siu
CSE
2009
IEEE
14 years 1 days ago
Prospector: Multiscale Energy Measurement of Networked Embedded Systems with Wideband Power Signals
Abstract—Today’s wirelessly networked embedded systems underlie a vast array of electronic devices, performing computation, communication, and input/output. A major design goal...
Kenji R. Yamamoto, Paul G. Flikkema