38 search results - page 1 / 8 » Serial-link bus: a low-power on-chip bus architecture |
DATE
2002
IEEE
13 years 9 months ago
2002
IEEE
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Interconnection networks in Systems-On-Chip begin to have a non-negligible impact on the power consumption of a whole system. This is because of increasing inter-wire capacitances...
DATE
2005
IEEE
13 years 6 months ago
2005
IEEE
In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consump...
VLSID
2006
IEEE
14 years 5 months ago
2006
IEEE
The two dominant architectural choices for implementing efficient communication fabrics for SoC's have been transaction-based buses and packet-based Networks-onChip (NoC). Bo...
DATE
2008
IEEE
13 years 6 months ago
2008
IEEE
We propose two crosstalk reducing coding schemes using ternary busses. In addition to low power consumption and reduced delay, our schemes offer other advantages over binary codin...