2 search results - page 1 / 1 » ShatterPB: symmetry-breaking for pseudo-Boolean formulas |
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
Many important tasks in circuit design and verification can be performed in practice via reductions to Boolean Satisfiability (SAT), making SAT a fundamental EDA problem. However ...
JEA
2007
13 years 4 months ago
2007