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» Shielding effect of on-chip interconnect inductance
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DAC
2001
ACM
10 years 2 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
DAC
1999
ACM
9 years 5 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ISQED
2007
IEEE
160views Hardware» more  ISQED 2007»
9 years 7 months ago
On-Chip Inductance in X Architecture Enabled Design
The inductance effects become significant for sub-100nm process designs due to increasing interconnect lengths, lower interconnect resistance values and fast signal transition tim...
Santosh Shah, Arani Sinha, Li Song, Narain D. Aror...
DAC
1998
ACM
10 years 2 months ago
Figures of Merit to Characterize the Importance of On-Chip Inductance
- A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicromete...
Yehea I. Ismail, Eby G. Friedman, José Luis...
ASPDAC
2007
ACM
122views Hardware» more  ASPDAC 2007»
9 years 5 months ago
Predicting the Performance and Reliability of Carbon Nanotube Bundles for On-Chip Interconnect
Single-walled carbon nanotube (SWCNT) bundles have the potential to provide an attractive solution for the resistivity and electromigration problems faced by traditional copper int...
Arthur Nieuwoudt, Mosin Mondal, Yehia Massoud
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