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» Side-Channel Leakage of Masked CMOS Gates
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CTRSA
2005
Springer
88views Cryptology» more  CTRSA 2005»
13 years 10 months ago
Side-Channel Leakage of Masked CMOS Gates
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per cloc...
Stefan Mangard, Thomas Popp, Berndt M. Gammel
CHES
2006
Springer
246views Cryptology» more  CHES 2006»
13 years 8 months ago
Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
This article starts with a discussion of three different attacks on masked AES hardware implementations. This discussion leads to the conclusion that glitches in masked circuits po...
Stefan Mangard, Kai Schramm
CHES
2006
Springer
88views Cryptology» more  CHES 2006»
13 years 8 months ago
Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
Recent research has shown that cryptographers with glitches are vulnerable in front of Side Channel Attacks (SCA). Since then, several methods, such as Wave Dynamic Differential Lo...
Zhimin Chen, Yujie Zhou
CHES
2009
Springer
239views Cryptology» more  CHES 2009»
14 years 5 months ago
Algebraic Side-Channel Attacks on the AES: Why Time also Matters in DPA
Algebraic side-channel attacks have been recently introduced as a powerful cryptanalysis technique against block ciphers. These attacks represent both a target algorithm and its ph...
François-Xavier Standaert, Mathieu Renauld,...
CHES
2006
Springer
152views Cryptology» more  CHES 2006»
13 years 8 months ago
Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
Daisuke Suzuki, Minoru Saeki