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ASPDAC
2006
ACM
117views Hardware» more  ASPDAC 2006»
10 years 9 months ago
Signal-path driven partition and placement for analog circuit
This paper advances a new methodology based on signal-path information to resolve the problem of device-level placement for analog layout. This methodology is mainly based on three...
Di Long, Xianlong Hong, Sheqin Dong
DAC
1995
ACM
10 years 6 months ago
Direct Performance-Driven Placement of Mismatch-Sensitive Analog Circuits
This paper presents a direct performance-driven placement algorithm for analog integrated circuits. The performance specications directly drive the layout tools without intermedi...
Koen Lampaert, Georges G. E. Gielen, Willy M. C. S...
ICCD
1997
IEEE
123views Hardware» more  ICCD 1997»
10 years 7 months ago
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement
Simulated annealing based standard cell placement for VLSI designs has long been acknowledged as a compute-intensive process. All previous work in parallel simulated annealing bas...
John A. Chandy, Prithviraj Banerjee
ISCAS
2007
IEEE
138views Hardware» more  ISCAS 2007»
10 years 9 months ago
A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
Henry H. Y. Chan, Zeljko Zilic
CLEIEJ
2010
10 years 10 days ago
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, ...
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