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CORR
2010
Springer
121views Education» more  CORR 2010»
13 years 4 months ago
Simulation vs. Equivalence
For several semirings S, two weighted finite automata with multiplicities in S are equivalent if and only if they can be connected by a chain of simulations. Such a semiring S is c...
Zoltán Ésik, Andreas Maletti
FCCM
2006
IEEE
131views VLSI» more  FCCM 2006»
13 years 10 months ago
Packet Switched vs. Time Multiplexed FPGA Overlay Networks
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
Nachiket Kapre, Nikil Mehta, Michael DeLorimier, R...
SPAA
1996
ACM
13 years 8 months ago
BSP vs LogP
A quantitative comparison of the BSP and LogP models of parallel computation is developed. We concentrate on a variant of LogP that disallows the so-called stalling behavior, alth...
Gianfranco Bilardi, Kieran T. Herley, Andrea Pietr...
CP
2005
Springer
13 years 10 months ago
2-Way vs. d-Way Branching for CSP
Abstract. Most CSP algorithms are based on refinements and extensions of backtracking, and employ one of two simple “branching schemes”: 2-way branching or d-way branching, fo...
Joey Hwang, David G. Mitchell
DAC
2006
ACM
14 years 5 months ago
Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification
Ever-growing complexity is forcing design to move above RTL. For example, golden functional models are being written as clearly as possible in software and not optimized or intend...
Xiushan Feng, Alan J. Hu