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ICCAD
2003
IEEE
111views Hardware» more  ICCAD 2003»
10 years 8 months ago
Simultaneous Analytic Area and Power Optimization for Repeater Insertion
We present an analytic formula for repeater insertion in global interconnects that simultaneously minimizes silicon device area and power dissipation for a given performance qrj,/...
Giuseppe S. Garcea, N. P. van der Meijs, Ralph H. ...
GLVLSI
2009
IEEE
112views VLSI» more  GLVLSI 2009»
10 years 6 months ago
Simultaneous shield and repeater insertion
Resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resulting in minimum c...
Renatas Jakushokas, Eby G. Friedman
TVLSI
2010
9 years 6 months ago
Resource Based Optimization for Simultaneous Shield and Repeater Insertion
A new approach for resource based optimization for high performance integrated circuits is presented. The methodology is applied to simultaneous shield and repeater insertion, resu...
Renatas Jakushokas, Eby G. Friedman
ISLPED
2007
ACM
138views Hardware» more  ISLPED 2007»
10 years 1 months ago
Power optimal MTCMOS repeater insertion for global buses
This paper addresses the problem of power-optimal repeater insertion for global buses in the presence of crosstalk noise. MTCMOS technique by inserting high-Vth sleep transistors ...
Hanif Fatemi, Behnam Amelifard, Massoud Pedram
JCP
2008
174views more  JCP 2008»
9 years 11 months ago
Simultaneous Sleep Transistor Insertion and Power Network Synthesis for Industrial Power Gating Designs
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
Kaijian Shi, Zhian Lin, Yi-Min Jiang, Lin Yuan
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