25 search results - page 1 / 5 » Simultaneous Gate and Interconnect Sizing for Circuit-Level ... |
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract—With delays due to the physical interconnect dominating the overall logic path delays, circuit-level delay optimization must take interconnect effects into account. Inst...
ASPDAC
1998
ACM
13 years 8 months ago
1998
ACM
- In this paper, we study the wire sizing and wire spacing problem for post-layout performance optimization under Elmore delay model. Both ground capacitance and coupled capacitanc...
ICCAD
2000
IEEE
13 years 8 months ago
2000
IEEE
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that ...
ICCAD
1998
IEEE
13 years 8 months ago
1998
IEEE
This paper considers simultaneous gate and wire sizing for general very large scale integrated (VLSI) circuits under the Elmore delay model. We present a fast and exact algorithm w...
ISCAS
2006
IEEE
13 years 10 months ago
2006
IEEE
– This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that crosscapacitances are ...