5 search results - page 1 / 1 » Simultaneous Retiming and Placement for Pipelined Netlists |
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
Although pipelining or C-slowing an FPGA-based application can potentially dramatically improve the performance, this poses a question for conventional reconfigurable architecture...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
FPGA application developers often attempt to use pipelining, Cslowing and retiming to improve the performance of their designs. Unfortunately, such registered netlists present a f...
DAC
2003
ACM
14 years 5 months ago
2003
ACM
Multiple clock cycles are needed to cross the global interconnects for multi-gigahertz designs in nanometer technologies. For synchronous designs, this requires retiming and pipel...
FPGA
2003
ACM
13 years 9 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
ISPD
2004
ACM
13 years 10 months ago
2004
ACM
As the CMOS technology is scaled into the dimension of nanometer, the clock frequencies and die sizes of ICs are shown to be increasing steadily [5]. Today, global wires that requ...