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MICRO
2009
IEEE
159views Hardware» more  MICRO 2009»
13 years 11 months ago
Adaptive line placement with the set balancing cache
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
Dyer Rolán, Basilio B. Fraguela, Ramon Doal...
HPCA
2006
IEEE
13 years 10 months ago
Increasing the cache efficiency by eliminating noise
Caches are very inefficiently utilized because not all the excess data fetched into the cache, to exploit spatial locality, is utilized. We define cache utilization as the percent...
Prateek Pujara, Aneesh Aggarwal
PLDI
2005
ACM
13 years 10 months ago
Code placement for improving dynamic branch prediction accuracy
Code placement techniques have traditionally improved instruction fetch bandwidth by increasing instruction locality and decreasing the number of taken branches. However, traditio...
Daniel A. Jiménez
CASES
2010
ACM
13 years 2 months ago
Improved procedure placement for set associative caches
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...
Yun Liang, Tulika Mitra
CGO
2004
IEEE
13 years 8 months ago
Exploring Code Cache Eviction Granularities in Dynamic Optimization Systems
Dynamic optimization systems store optimized or translated code in a software-managed code cache in order to maximize reuse of transformed code. Code caches store superblocks that...
Kim M. Hazelwood, James E. Smith