49 search results - page 2 / 10 » Sizing of Processing Arrays for FPGA-Based Computation |
ICPPW
2006
IEEE
13 years 10 months ago
2006
IEEE
Embedded computing architectures can be designed to meet a variety of application specific requirements. However, optimized hardware can require compiler support to realize the po...
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
Historically, most radar sensor array processing has been implemented using dedicated and specialized processing systems. This approach was necessary because the algorithm computa...
IPPS
1999
IEEE
13 years 8 months ago
1999
IEEE
Real-time image processing applications have tremendous computational workloads and I/O throughput requirements. Operation in mobile, portable devices poses stringent resource limi...
ASAP
2006
IEEE
13 years 10 months ago
2006
IEEE
Abstract – The storage requirements in data-dominant signal processing systems, whose behavior is described by arraybased, loop-organized algorithmic specifications, have an imp...
ICPP
2008
IEEE
13 years 11 months ago
2008
IEEE
This paper presents a novel stateless, virtualized communication engine for sub-microsecond latency. Using a Field-Programmable-Gate-Array (FPGA) based prototype we show a latency...