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TC
2008
13 years 5 months ago
Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
ICAS
2005
IEEE
130views Robotics» more  ICAS 2005»
13 years 10 months ago
Reno Friendly TCP Westwood based on Router Buffer Estimation
— TCP Reno versions are widely used in current network, however it has been actualized that their throughput deteriorates in high-speed network and wireless environments. To over...
Kazumi Kaneko, Jiro Katto
INFOCOM
2006
IEEE
13 years 11 months ago
Routers with Very Small Buffers
Abstract— Internet routers require buffers to hold packets during times of congestion. The buffers need to be fast, and so ideally they should be small enough to use fast memory ...
Mihaela Enachescu, Yashar Ganjali, Ashish Goel, Ni...
GLOBECOM
2007
IEEE
13 years 9 months ago
Mean-Field Analysis of Buffer Sizing
Two schools of thoughts have emerged over the recent debate on internet router buffer sizing. One school argues that the presence of a large number of flows leads to traffic desync...
Mei Wang
MICRO
2006
IEEE
98views Hardware» more  MICRO 2006»
13 years 11 months ago
ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers
The advent of deep sub-micron technology has recently highlighted the criticality of the on-chip interconnects. As diminishing feature sizes have led to increases in global wiring...
Chrysostomos Nicopoulos, Dongkook Park, Jongman Ki...