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GECCO
2005
Springer
152views Optimization» more  GECCO 2005»
13 years 11 months ago
Multi-level genetic algorithm (MLGA) for the construction of clock binary tree
The clock signal and clock skew become more and more important for the circuit performance. Since there are salient shortcomings in the conventional topology construction algorith...
Guofang Nan, Minqiang Li, Jisong Kou
ICCAD
2010
IEEE
158views Hardware» more  ICCAD 2010»
13 years 3 months ago
Novel binary linear programming for high performance clock mesh synthesis
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...
Minsik Cho, David Z. Pan, Ruchir Puri
DAMON
2006
Springer
13 years 7 months ago
B-tree indexes, interpolation search, and skew
Recent performance improvements in storage hardware have benefited bandwidth much more than latency. Among other implications, this trend favors large B-tree pages. Recent perform...
Goetz Graefe
ISCAS
1995
IEEE
70views Hardware» more  ISCAS 1995»
13 years 9 months ago
Minimum-Cost Bounded-Skew Clock Routing
In this paper, we present a new clock routing algorithm which minimizes total wirelength under any given path-length skew bound. The algorithm constructs a bounded-skew tree (BST)...
Jason Cong, Cheng-Kok Koh