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» Sleep transistor distribution in row-based MTCMOS designs
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ISQED
2010
IEEE
227views Hardware» more  ISQED 2010»
10 years 4 months ago
Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks
Leakage power has grown significantly and is a major challenge in SoC design. Among SoC's components, clock distribution network power accounts for a large portion of chip po...
Houman Homayoun, Shahin Golshan, Eli Bozorgzadeh, ...
DAC
2002
ACM
10 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
ICCAD
2007
IEEE
86views Hardware» more  ICCAD 2007»
10 years 6 months ago
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
—During the power mode transition, a large surge current may lead to the malfunctions in a power-gating design. In this paper, we introduce several important properties of the s...
Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-C...
ISLPED
2003
ACM
90views Hardware» more  ISLPED 2003»
10 years 3 months ago
Understanding and minimizing ground bounce during mode transition of power gating structures
We introduce and analyze the ground bounce due to power mode transition in power gating structures. To reduce the ground bounce, we propose novel power gating structures in which ...
Suhwan Kim, Stephen V. Kosonocky, Daniel R. Knebel
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