9 search results - page 1 / 2 » Soft error benchmarking of L2 caches with PARMA |
SIGMETRICS
2011
ACM
12 years 7 months ago
2011
ACM
The amount of charge stored in an SRAM cell shrinks rapidly with each technology generation thus increasingly exposing caches to soft errors. Benchmarking the FIT rate of caches d...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Memory elements are the most vulnerable system component to soft errors. Since memory elements in cache arrays consume a large fraction of the die in modern microprocessors, the p...
TCAD
2008
13 years 4 months ago
2008
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
ISPASS
2005
IEEE
13 years 10 months ago
2005
IEEE
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
HPCA
2005
IEEE
14 years 4 months ago
2005
IEEE
This paper studies the impact of L2 cache sharing on threads that simultaneously share the cache, on a Chip Multi-Processor (CMP) architecture. Cache sharing impacts threads non-u...