6 search results - page 1 / 2 » Soft error reduction in combinational logic using gate resiz... |
ICCAD
2006
IEEE
14 years 1 months ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
DSN
2008
IEEE
13 years 6 months ago
2008
IEEE
The combination of continued technology scaling and increased on-chip transistor densities has made vulnerability to radiation induced soft errors a significant design concern. In...
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
ICCAD
2004
IEEE
14 years 1 months ago
2004
IEEE
— A radiation hardening technique for combinational logic circuits is described. The key idea is to exploit the asymmetric logical masking probabilities of gates, hardening gates...
DAC
2008
ACM
14 years 5 months ago
2008
ACM
Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking ...