Sciweavers

9 search results - page 1 / 2
» Soft-OLP: Improving Hardware Cache Performance through Softw...
Sort
View
IEEEPACT
2009
IEEE
13 years 11 months ago
Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning
—Performance degradation of memory-intensive programs caused by the LRU policy’s inability to handle weaklocality data accesses in the last level cache is increasingly serious ...
Qingda Lu, Jiang Lin, Xiaoning Ding, Zhao Zhang, X...
ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
14 years 1 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
EDBT
2010
ACM
155views Database» more  EDBT 2010»
13 years 7 months ago
Suffix tree construction algorithms on modern hardware
Suffix trees are indexing structures that enhance the performance of numerous string processing algorithms. In this paper, we propose cache-conscious suffix tree construction algo...
Dimitris Tsirogiannis, Nick Koudas
HPCA
2008
IEEE
14 years 4 months ago
Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
Jiang Lin, Qingda Lu, Xiaoning Ding, Zhao Zhang, X...
DATE
2009
IEEE
132views Hardware» more  DATE 2009»
13 years 11 months ago
Power and performance of read-write aware Hybrid Caches with non-volatile memories
—Caches made of non-volatile memory technologies, such as Magnetic RAM (MRAM) and Phase-change RAM (PRAM), offer dramatically different power-performance characteristics when com...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Yu...