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    » Soft-output sphere decoding: algorithms and VLSI implementat...
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    ISCAS
    2002
    IEEE
    143views Hardware» more  ISCAS 2002»
    Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000
    13 years 10 months ago
    Analysis of EBCOT decoding algorithm and its VLSI implementation for JPEG 2000
    Download  video.ee.ntu.edu.tw
    Hong-Hui Chen, Chung-Jr Lian, Te-Hao Chang, Liang-...
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    NIPS
    1996
    110views Information Technology» more  NIPS 1996»
    A Micropower Analog VLSI HMM State Decoder for Wordspotting
    13 years 7 months ago
    A Micropower Analog VLSI HMM State Decoder for Wordspotting
    Download  www.cs.berkeley.edu
    We describe the implementation of a hidden Markov model state decoding system, a component for a wordspotting speech recognition system. The key specification for this state decod...
    John Lazzaro, John Wawrzynek, Richard Lippmann
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    ISLPED
    1998
    ACM
    84views Hardware» more  ISLPED 1998»
    Low power architecture of the soft-output Viterbi algorithm
    13 years 10 months ago
    Low power architecture of the soft-output Viterbi algorithm
    Download  www.ee.virginia.edu
    CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
    David Garrett, Mircea R. Stan
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    ICC
    2007
    IEEE
    121views Communications» more  ICC 2007»
    On the Expected Complexity Analysis of a Generalized Sphere Decoding Algorithm for Underdetermined Linear Communication Systems
    14 years 2 days ago
    On the Expected Complexity Analysis of a Generalized Sphere Decoding Algorithm for Underdetermined Linear Communication Systems
    Download  www.prism.uvsq.fr
    This paper presents an analytical approach to evaluate the expected complexity of a generalized sphere decoding (GSD) algorithm, GSDλ − , for underdetermined integer leastsquare...
    Ping Wang, Tho Le-Ngoc
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    ISCAS
    1993
    IEEE
    125views Hardware» more  ISCAS 1993»
    A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
    13 years 10 months ago
    A VLSI Implementation of a Cascade Viterbi Decoder with Traceback
    Download  www.eecg.toronto.edu
    - A novel VLSI implementation of the Viterbi algorithm based on a cascade architecture is presented. Survivor sequence memory management is implemented using a new single read poin...
    Gennady Feygin, Paul Chow, P. Glenn Gulak, John Ch...
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