15 search results - page 3 / 3 » Software Synthesis of Process-Based Concurrent Programs |
CODES
2005
IEEE
13 years 11 months ago
2005
IEEE
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
EMSOFT
2004
Springer
13 years 10 months ago
2004
Springer
Esterel is a system-level language for the modelling, verification and synthesis of control dominated (reactive) embedded systems. Existing Esterel compilers generate intermediat...
EUROMICRO
2000
IEEE
13 years 9 months ago
2000
IEEE
In this paper we propose a high-level description of the behavior of digital systems. Behaviors are specified with a graphical synchronous model: “SyncCharts”. SyncCharts supp...
FMSD
2006
13 years 5 months ago
2006
Synchronous specifications are appealing in the design of large scale hardware and software systems because of their properties that facilitate verification and synthesis. When the...
EMSOFT
2004
Springer
13 years 10 months ago
2004
Springer
Data flow process networks are a good model of computation for streaming multimedia applications incorporating audio, video and/or graphics streams. Process networks are concurre...