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DAC
2004
ACM
14 years 6 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
IISWC
2008
IEEE
13 years 11 months ago
Evaluating the impact of dynamic binary translation systems on hardware cache performance
Dynamic binary translation systems enable a wide range of applications such as program instrumentation, optimization, and security. DBTs use a software code cache to store previou...
Arkaitz Ruiz-Alvarez, Kim M. Hazelwood
RT
1999
Springer
13 years 9 months ago
Interactive Rendering using the Render Cache
Interactive rendering requires rapid visual feedback. The render cache is a new method for achieving this when using high-quality pixel-oriented renderers such as ray tracing that...
Bruce Walter, George Drettakis, Steven G. Parker
CGO
2003
IEEE
13 years 8 months ago
METRIC: Tracking Down Inefficiencies in the Memory Hierarchy via Binary Rewriting
In this paper, we present METRIC, an environment for determining memory inefficiencies by examining data traces. METRIC is designed to alter the performance behavior of applicatio...
Jaydeep Marathe, Frank Mueller, Tushar Mohan, Bron...
SIGMETRICS
2008
ACM
214views Hardware» more  SIGMETRICS 2008»
13 years 5 months ago
HMTT: a platform independent full-system memory trace monitoring system
Memory trace analysis is an important technology for architecture research, system software (i.e., OS, compiler) optimization, and application performance improvements. Many appro...
Yungang Bao, Mingyu Chen, Yuan Ruan, Li Liu, Jianp...