72 search results - page 14 / 15 » Software model checking via large-block encoding |
CAV
1998
Springer
13 years 9 months ago
1998
Springer
As a pedagogical exercise in ACL2, we formalize and prove the correctness of a write invalidate cache scheme. In our formalization, an arbitrary number of processors, each with its...
VMCAI
2010
Springer
14 years 16 days ago
2010
Springer
This paper upgrades Regular Linear Temporal Logic (RLTL) with past operators and complementation. RLTL is a temporal logic that extends the expressive power of linear temporal logi...
AC
2000
Springer
13 years 5 months ago
2000
Springer
nvented abstract representations of value. As time passed, representations of value became more abstract, progressing from barter through bank notes, payment orders, checks, credit...
CASES
2009
ACM
14 years 2 days ago
2009
ACM
Accurate estimation of the tick length of a synchronous program is essential for efficient and predictable implementations that are devoid of timing faults. The techniques to dete...
FMSD
2007
13 years 5 months ago
2007
Symbolic techniques based on Binary Decision Diagrams (BDDs) are widely employed for reasoning about temporal properties of hardware circuits and synchronous controllers. However, ...