23 search results - page 1 / 5 » Sparse Matrix-Vector multiplication on FPGAs |
FCCM
2006
IEEE
13 years 10 months ago
2006
IEEE
We present an architecture and an implementation of an FPGA-based sparse matrix-vector multiplier (SMVM) for use in the iterative solution of large, sparse systems of equations ar...
FCCM
2007
IEEE
13 years 6 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
FPGA
2005
ACM
13 years 9 months ago
2005
ACM
Floating-point Sparse Matrix-Vector Multiplication (SpMXV) is a key computational kernel in scientific and engineering applications. The poor data locality of sparse matrices sig...
ERSA
2010
13 years 2 months ago
2010
Cache-based, general purpose CPUs perform at a small fraction of their maximum floating point performance when executing memory-intensive simulations, such as those required for sp...
CATA
2010
13 years 5 months ago
2010
Computations with sparse matrices on "multicore cache based" computers are affected by the irregularity of the problem at hand, and performance degrades easily. In this ...