8 search results - page 1 / 2 » Speculative Loop-Pipelining in Binary Translation for Hardwa... |
TCAD
2008
13 years 4 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
DATE
2005
IEEE
13 years 10 months ago
2005
IEEE
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
ISCA
2006
IEEE
13 years 10 months ago
2006
IEEE
A Co-Designed Virtual Machine allows designers to implement a processor via a combination of hardware and software. Dynamic binary translation converts code written for a conventi...
ISCA
2008
IEEE
13 years 11 months ago
2008
IEEE
Performance improvement solely through transistor scaling is becoming more and more difficult, thus it is increasingly common to see domain specific accelerators used in conjunc...