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» Speculative Parallel Threading Architecture and Compilation
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IPPS
2009
IEEE
14 years 20 days ago
Implementing and evaluating multithreaded triad census algorithms on the Cray XMT
Commonly represented as directed graphs, social networks depict relationships and behaviors among social entities such as people, groups, and organizations. Social network analysi...
George Chin Jr., Andrès Márquez, Sut...
MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
13 years 6 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
ICS
1999
Tsinghua U.
13 years 10 months ago
Classifying load and store instructions for memory renaming
Memory operations remain a significant bottleneck in dynamically scheduled pipelined processors, due in part to the inability to statically determine the existence of memory addr...
Glenn Reinman, Brad Calder, Dean M. Tullsen, Gary ...
DATE
2008
IEEE
156views Hardware» more  DATE 2008»
14 years 15 days ago
Transparent Reconfigurable Acceleration for Heterogeneous Embedded Applications
Embedded systems are becoming increasingly complex. Besides the additional processing capabilities, they are characterized by high diversity of computational models coexisting in ...
Antonio Carlos Schneider Beck, Mateus B. Rutzig, G...
DAC
2008
ACM
13 years 7 months ago
Application mapping for chip multiprocessors
The problem attacked in this paper is one of automatically mapping an application onto a Network-on-Chip (NoC) based chip multiprocessor (CMP) architecture in a locality-aware fas...
Guangyu Chen, Feihui Li, Seung Woo Son, Mahmut T. ...