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HPCA
1998
IEEE
13 years 8 months ago
Speculative Versioning Cache
Dependences among loads and stores whose addresses are unknown hinder the extraction of instruction level parallelism during the execution of a sequential program. Such ambiguous ...
Sridhar Gopal, T. N. Vijaykumar, James E. Smith, G...
HPCA
2003
IEEE
14 years 4 months ago
Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors
Thread-level speculation provides architectural support to aggressively run hard-to-analyze code in parallel. As speculative tasks run concurrently, they generate unsafe or specul...
María Jesús Garzarán, Milos P...
ICCD
2006
IEEE
92views Hardware» more  ICCD 2006»
14 years 1 months ago
Fast Speculative Address Generation and Way Caching for Reducing L1 Data Cache Energy
— L1 data caches in high-performance processors continue to grow in set associativity. Higher associativity can significantly increase the cache energy consumption. Cache access...
Dan Nicolaescu, Babak Salamat, Alexander V. Veiden...
TPDS
2008
150views more  TPDS 2008»
13 years 4 months ago
Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices
This paper presents the Mitosis framework, which is a combined hardware-software approach to speculative multithreading, even in the presence of frequent dependences among threads....
Carlos Madriles, Carlos García Quiño...
SBACPAD
2004
IEEE
105views Hardware» more  SBACPAD 2004»
13 years 6 months ago
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes br...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...