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HPCA
2008
IEEE
14 years 18 days ago
Speculative instruction validation for performance-reliability trade-off
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
ICDCN
2012
Springer
12 years 1 months ago
Lifting the Barriers - Reducing Latencies with Transparent Transactional Memory
Synchronization in distributed systems is expensive because, in general, threads must stall to obtain a lock or to operate on volatile data. Transactional memory, on the other hand...
Annette Bieniusa, Thomas Fuhrmann
ICPP
2009
IEEE
14 years 24 days ago
Code Semantic-Aware Runahead Threads
Memory-intensive threads can hoard shared resources without making progress on a multithreading processor (SMT), thereby hindering the overall system performance. A recent promisi...
Tanausú Ramírez, Alex Pajuelo, Olive...
IEEEPACT
2007
IEEE
14 years 14 days ago
The OpenTM Transactional Application Programming Interface
Transactional Memory (TM) simplifies parallel programming by supporting atomic and isolated execution of user-identified tasks. To date, TM programming has required the use of l...
Woongki Baek, Chi Cao Minh, Martin Trautmann, Chri...
JOT
2007
99views more  JOT 2007»
13 years 6 months ago
The Parametric Singleton Design Pattern
The parametric singleton design pattern combines the singleton design pattern with a parameter that enables unique creation of instances of a class. These instances are cached in ...
Douglas A. Lyon, Francisco Castellanos