30 search results - page 4 / 6 » Speeding up Mutual Information Computation Using NVIDIA CUDA... |
CF
2009
ACM
14 years 8 days ago
2009
ACM
In this paper, we compare the architectural perspectives of the Wave Field Synthesis (WFS) 3D-audio algorithm mapped on three different platforms: a General Purpose Processor (GP...
ARC
2012
Springer
12 years 1 months ago
2012
Springer
Iterative numerical algorithms with high memory bandwidth requirements but medium-size data sets (matrix size ∼ a few 100s) are highly appropriate for FPGA acceleration. This pap...
ASPLOS
2010
ACM
14 years 8 days ago
2010
ACM
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
HPCA
2000
IEEE
13 years 10 months ago
2000
IEEE
Memorylatency isbecominganincreasingly importantperformance bottleneck, especially in multiprocessors. One technique for tolerating memory latency is multithreading, whereby we sw...
ICCAD
2002
IEEE
14 years 2 months ago
2002
IEEE
The simulation of on-chip inductance using PEEC-based circuit analysis methods often requires the solution of a subproblem where an extracted inductance matrix must be multiplied ...