23 search results - page 1 / 5 » Speeding up SystemC simulation through process splitting |
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper presents a new approach that can be used to speed up SystemC simulations by automatically optimizing the model for simulation. The work addresses the inefficiency of th...
FDL
2003
IEEE
13 years 10 months ago
2003
IEEE
This paper proposes a methodology for the extension of SystemC to mixed signal systems. An oscillator made up of an inverter chain has been used to test the accuracy and stability...
HOTI
2005
IEEE
13 years 10 months ago
2005
IEEE
: The exposed memory hierarchies employed in many network processors (NPs) are expensive in terms of meeting the worst-case processing requirement. Moreover, it is difficult to ef...
TRIDENTCOM
2005
IEEE
13 years 10 months ago
2005
IEEE
Today’s Internet backbone networking devices need to be tested under realistic traffic conditions at transmission rates of OC-48 and above. While commercially available synthet...
MICRO
2006
IEEE
13 years 4 months ago
2006
IEEE
In the past few years, several research works have demonstrated that sampling can drastically speed up architecture simulation, and several of these sampling techniques are already...