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DAC
2006
ACM
14 years 5 months ago
Standard cell characterization considering lithography induced variations
As VLSI technology scales toward 65nm and beyond, both timing and power performance of integrated circuits are increasingly affected by process variations. In practice, people oft...
Ke Cao, Sorin Dobre, Jiang Hu
ISQED
2007
IEEE
182views Hardware» more  ISQED 2007»
13 years 10 months ago
Defect or Variation? Characterizing Standard Cell Behavior at 90nm and below
Historically, design margin and defects have been viewed as different topics, one part of design and the other part of test. Shrinking process geometries are making the two part o...
Robert C. Aitken
ICCD
2007
IEEE
111views Hardware» more  ICCD 2007»
14 years 1 months ago
On modeling impact of sub-wavelength lithography on transistors
As the VLSI technology marches beyond 65 and 45nm process technologies, variation in gate length has a direct impact on leakage and performance of CMOS transistors. Due to sub-wav...
Aswin Sreedhar, Sandip Kundu
ISQED
2011
IEEE
329views Hardware» more  ISQED 2011»
12 years 8 months ago
New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm
The extent to which the 6T SRAM bit cell can be perpetuated through continued scaling is of enormous technological and economic importance. Understanding the growing limitations i...
Randy W. Mann, Benton H. Calhoun
ASPDAC
2007
ACM
117views Hardware» more  ASPDAC 2007»
13 years 8 months ago
A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms
An accurate model is presented to calculate the short circuit energy dissipation of logic cells. The short circuit current is highly dependent on the input and output voltage valu...
Hanif Fatemi, Shahin Nazarian, Massoud Pedram