25 search results - page 1 / 5 » Standby Leakage Power Reduction Technique for Nanoscale CMOS... |
TIM
2010
12 years 11 months ago
2010
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
ISCAS
2007
IEEE
13 years 10 months ago
2007
IEEE
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
DAC
2004
ACM
13 years 8 months ago
2004
ACM
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
ISLPED
1999
ACM
13 years 8 months ago
1999
ACM
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
ICCAD
2005
IEEE
13 years 10 months ago
2005
IEEE
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...