Sciweavers

Share
25 search results - page 1 / 5
» Standby Leakage Power Reduction Technique for Nanoscale CMOS...
Sort
View
TIM
2010
294views Education» more  TIM 2010»
9 years 6 months ago
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
In this paper, a novel low-power design technique is proposed to minimize the standby leakage power in nanoscale CMOS very large scale integration (VLSI) systems by generating the ...
HeungJun Jeon, Yong-Bin Kim, Minsu Choi
ISCAS
2007
IEEE
126views Hardware» more  ISCAS 2007»
10 years 5 months ago
Optimal Body Biasing for Minimum Leakage Power in Standby Mode
— This paper describes a new power minimizing method by optimizing supply voltage control and minimizing leakage in active and standby modes, respectively. In the active mode, th...
Kyung Ki Kim, Yong-Bin Kim
DAC
2004
ACM
10 years 3 months ago
Leakage in nano-scale technologies: mechanisms, impact and design considerations
The high leakage current in nano-meter regimes is becoming a significant portion of power dissipation in CMOS circuits as threshold voltage, channel length, and gate oxide thickne...
Amit Agarwal, Chris H. Kim, Saibal Mukhopadhyay, K...
ISLPED
1999
ACM
177views Hardware» more  ISLPED 1999»
10 years 3 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V ...
Vijay Sundararajan, Keshab K. Parhi
ICCAD
2005
IEEE
199views Hardware» more  ICCAD 2005»
10 years 5 months ago
FinFETs for nanoscale CMOS digital integrated circuits
Suppression of leakage current and reduction in device-todevice variability will be key challenges for sub-45nm CMOS technologies. Non-classical transistor structures such as the ...
Tsu-Jae King
books